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lf to 750 mhz, digitally controlled vga data sheet ad8370 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005-2011 analog devices, inc. all rights reserved. features programmable low and high gain (<2 db resolution) low range: ?11 db to +17 db high range: 6 db to 34 db differential input and output 200 differential input 100 differential output 7 db noise figure @ maximum gain two-tone ip3 of 35 dbm @ 70 mhz ?3 db bandwidth of 750 mhz 40 db precision gain range serial 8-bit digital interface wide input dynamic range power-down feature single 3 v to 5 v supply applications differential adc drivers if sampling receivers rf/if gain stages cable and video applications saw filter interfacing single-ended-to-differential conversion general description the ad8370 is a low cost, digitally controlled, variable gain amplifier (vga) that provides precision gain control, high ip3, and low noise figure. the excellent distortion performance and wide bandwidth make the ad8370 a suitable gain control device for modern receiver designs. for wide input, dynamic range applications, the ad8370 provides two input ranges: high gain mode and low gain mode. a vernier, 7-bit, transconductance (g m ) stage provides 28 db of gain range at better than 2 db resolution and 22 db of gain range at better than 1 db resolution. a second gain range, 17 db higher than the first, can be selected to provide improved noise performance. the ad8370 is powered on by applying the appropriate logic level to the pwup pin. when powered down, the ad8370 consumes less than 4 ma and offers excellent input to output isolation. the gain setting is preserved when operating in a power-down mode. functional block diagram inhi inlo ophi oplo vcco ocom icom vocm pwup vcco ocom vcci icom bias cell shift register and latches pre amp transconductance output amp 11 6 1 16 4 14 13 12 5 9 8 3 2 10 7 15 data clck ltch ad8370 03692-001 figure 1. 0 10 20 30 40 50 60 70 ?30 ?20 ?10 0 10 20 30 40 voltage gain (db) voltage gain (v/v) 0 10203040 60 100 50 70 80 90 110 120 130 gain code 03692-002 code = last 7 bits of gain code (no msb) high gain mode high gain mode low gain mode low gain mode ? gain ? code ? 0.409 ? gain ? code ? 0.059 figure 2. gain vs. gain code at 70 mhz gain control of the ad8370 is through a serial 8-bit gain control word. the msb selects between the two gain ranges, and the remaining 7 bits adjust the overall gain in precise linear gain steps. fabricated on the adi high speed xfcb process, the high bandwidth of the ad8370 provides high frequency and low distortion. the quiescent current of the ad8370 is 78 ma typically. the ad8370 amplifier comes in a compact, thermally enhanced 16-lead tssop package and operates over the temperature range of ?40c to +85c.
ad8370 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 gener al description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 s pecifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin con figuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 13 block architecture ...................................................................... 13 preamplifier ................................................................................. 13 transconductance stage ............................................................ 13 output amplifier ........................................................................ 14 digital interface and timing .................................................... 14 applications ..................................................................................... 15 basic connections ...................................................................... 15 gain codes .................................................................................. 15 power - up feature ....................................................................... 15 choosing between gain ranges .............................................. 16 layout and operating considerations .................................... 16 package considerations ............................................................. 17 single - ended - to - differential conversion ............................... 17 dc - coupled operation ............................................................. 18 adc interfacing ......................................................................... 19 3 v operation ............................................................................. 20 evaluation board and software .................................................... 22 appendix ......................................................................................... 25 characterization equipment ..................................................... 25 composite waveform assumption .......................................... 25 definitions of selected parameters .......................................... 25 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 12 / 11 rev. a to rev. b ch anges to slew rate parameters, table 1 .................................... 3 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 28 7/05 rev. 0 to rev. a changes to features .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to figure 11 and figure 15 ............................................... 8 added fig ure 12; renumbered sequentially ................................ 8 added figure 16; renumbered sequentially ................................ 9 changes to evaluation board and software section .................. 22 changes to figure 60 ...................................................................... 23 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 28 1/04 revision 0: initial version
data sheet ad8370 rev. b | page 3 of 28 specifications v s = 5 v, t = 25c, z s = 200 ?, z l = 100 ? at gain code hg127, 70 mhz, 1 v p - p differential output, unless otherwise noted. table 1 . parameter conditions min typ max unit dynamic performance ? 3 db bandwidth v out < 1 v p -p 750 mhz slew rate gai n code hg127, r l = 1 k ? , ad8370 in compression 5. 75 v/ns gain code lg127, rl = 1 k?, v out = 2 v p -p 3 .5 v/ns input stage pins inhi and ihlo maximum input gain code lg2, 1 db compression 3.2 v p -p input resistance differential 200 ? common - mode input range 3.2 v p -p cmrr differential, f = 10 mhz, gain code lg127 77 db input noise spectral density 1.9 nv/ hz gain maximum voltage gain high gain mode gain code = hg127 34 db 52 v/v low gain mode gain code = lg12 7 17 db 7.4 v/v minimum voltage gain high gain mode gain code = hg1 ? 8 db 0.4 v/v low gain mode gain code = lg1 ? 25 db 0.06 v/v gain step size high gain mode 0.408 (v/v)/code low gain mode 0.056 (v/v)/code gain temper ature sensitivity gain code = hg127 C2 mdb/ c step response for 6 db gain step, settled to 10% of final value 20 ns output interface pins ophi and oplo output voltage swing r l 1 k ? (1 db compression) 8.4 v p -p output resistance diff erential 95 ? output differential offset v inhi = v inlo , over all gain codes 60 mv noise/harmonic performance 10 mhz gain flatness within 10 mhz of 10 mhz 0.01 db noise figure 7.2 db second harmonic 1 v out = 2 v p - p ? 77 dbc third harmonic 1 v out = 2 v p -p ? 77 dbc output ip3 35 dbm output 1 db compression point 17 dbm 70 mhz gain flatness within 10 mhz of 70 mhz 0.02 db noise figure 7.2 db second harmonic 1 v out = 2 v p -p ? 65 dbc third harmonic 1 v out = 2 v p -p ? 62 dbc output ip3 35 dbm output 1 db compression point 17 dbm
ad8370 data sheet rev. b | page 4 of 28 parameter conditions min typ max unit 140 mhz gain flatness within 10 mhz of 140 mhz 0.03 db noise figure 7.2 db second harmonic 1 v out = 2 v p -p ? 54 dbc third harmonic 1 v out = 2 v p - p ? 50 dbc output ip3 33 dbm output 1 db compression point 17 dbm 190 mhz gain flatness within 10 mhz of 240 mhz 0.03 db noise figure 7.2 db second harmonic 1 v out = 2 v p -p ? 43 dbc third harmonic 1 v out = 2 v p -p ? 43 dbc o utput ip3 33 dbm output 1 db compression point 17 dbm 240 mhz gain flatness within 10 mhz of 240 mhz 0.04 db noise figure 7.4 db second harmonic 1 v out = 2 v p -p C 28 dbc third harmonic 1 v out = 2 v p -p C 33 dbc output ip3 32 dbm output 1 db compression point 17 dbm 380 mhz gain flatness within 10 mhz of 240 mhz 0.04 db noise figure 8.1 db output ip3 27 dbm output 1 db compression poi nt 14 dbm power - interface supply voltage 3.0 2 5.5 v quiescent current 3 pwup high, gc = lg127, r l = , 4 seconds after power - on, thermal connection made to exposed paddle under device 72.5 79 85.5 ma vs. temperature 4 ? 40c t a + 85c 105 ma total supply current pwup high, v out = 1 v p - p, z l = 100 ? reactive , gc = lg127 (includes load current) 82 ma power - down current pwup low 3.7 ma vs. temperature 4 ? 40c t a + 85c 5 ma power - up interfac e pin pwup power - up threshold 4 voltage to enable the device 1.8 v power - down threshold 4 voltage to disable the device 0.8 v pwup input bias current pwup = 0 v 400 na gain control interface pins clck, data, and ltch v ih 4 voltage for a logic high 1.8 v v il 4 voltage for a logic low 0.8 v input bias current 900 na 1 refer to figure 22 for performance into a lighter load. 2 see the 3 v operation section for more information. 3 minimum and maximum specified limits for this parameter are guaranteed by pr oduction test. 4 minimum or maximum specified limit for this parameter is a 6 - sigma value and not guaranteed by production test.
data sheet ad8370 rev. b | page 5 of 28 absolute maximum rat ings table 2 . parameter rating supply voltage, v s 5.5 v pwup, data, clck, ltch v s + 500 mv differential input voltage, v inhi C v inlo 2 v common - mode input voltage, v inhi or v inlo, with respect to icom or ocom v s + 500 mv (max), v icom C 500 mv, v ocom C 500 mv (min) internal power dissipation 575 mw ja (exposed paddle soldered d own) 30 c/w ja (exposed paddle not soldered do wn) 95 c/w jc (at exposed pad dle) 9 c/w maximum junction temperature 150 c operating temperature range ?40 c to +85 c storage temperature range ?65 c to +150 c lead tempera ture range (soldering 60 sec) 235 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as h igh as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic di scharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8370 data sheet rev. b | page 6 of 28 pin configuration and function descripti ons 03692-003 6 7 8 11 10 9 ad8370 top view (not to scale) 2 3 4 5 15 14 1 16 13 12 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo figure 3 .16 - lead tssop table 3 . pin function descriptions pin no. mnemonic description 1 inhi balanced differential input. internally biased. 2, 15, paddle icom input common. connect to a low impedance ground. this node is also connected to the exposed pad on the bottom of the device. 3 vcci input positive supply. 3.0 v to 5.5 v. should be properly bypassed. 4 pwup power enable pin. device is operational when pwup is pulled high. 5 vocm common - mode output voltage pin. the midsupply ((v vcco ? v ocom )/2) common - mode voltage is delivered to this pin for external bypassing for additional common - mode supply decoupling. this can be achieved with a bypass capacitor to ground. this pin is an output only and is not to be driven externally. 6, 11 vc co output positive supply. 3.0 v to 5.5 v. should be properly bypassed. 7, 10 ocom output common. connect to a low impedance ground. 8 ophi balanced differential output. biased to midsupply. 9 oplo balanced differential output. biased to midsupply. 12 ltc h serial data latch pin. serial data is clocked into the shift register via the data pin when ltch is low. data in shift register is latched on the next high - going edge. 13 clck serial clock input pin. 14 data serial data input pin. 16 inlo balance d differential input. internally biased.
data sheet ad8370 rev. b | page 7 of 28 typical performance characteristics v s = 5 v, z s = 200 ?, z l = 100 ?, t = 25c, unless otherwise noted. 0 10 20 30 40 50 60 70 ?30 ?20 ?10 0 10 20 30 40 voltage gain (db) voltage gain (v/v) 0 10 20 30 40 60 100 50 70 80 90 110 120 130 gain code 03692-004 code = last 7 bits of gain code (no msb) high gain mode high gain mode low gain mode low gain mode ? gain ? code ? 0.409 ? gain ? code ? 0.059 figure 4 . gain vs. gain code at 70 mhz 5 10 15 20 25 30 35 40 ?5 0 5 10 15 20 25 30 0 20 40 60 80 100 120 140 03692-068 high gain mode low gain mode shading indicates 3 from the mean. data based on 30 parts from two batch lots. gain code output ip3 (dbm) output ip3 (dbv rms) figure 5. output third - order intercept vs. gain code at 70 mhz 5 10 15 20 25 30 noise figure (db) 35 40 45 0 20 40 60 80 100 120 140 gain code 03692-006 high gain mode 380mhz 380mhz 70mhz 70mhz low gain mode figure 6 . noise figure vs. gain code at 70 mhz ?10 ?5 0 5 10 15 20 25 30 35 40 voltage gain (db) frequency (mhz) 10 100 1000 03692-007 hg77 hg127 lg90 lg9 lg18 lg127 hg102 hg18 lg36 hg51 hg25 hg9 hg3 high gain codes shown with dashed lines low gain codes shown with solid lines figure 7 . frequency response vs. gain code output ip3 (dbm) +25c frequency (mhz) output ip3 (dbm) ?40 c, +85c 10 15 20 25 30 35 40 20 25 30 35 40 45 50 200 150 50 100 0 250 300 350 400 03692-069 +25c unit conversion note for 100? load: dbvrms = dbm?10db +85c ?40c shading indicates 3 from the mean. data based on 30 parts from two batch lots. figure 8 . output third - or der intercept vs. frequency at maximum gain 0 5 10 15 20 25 noise figure (db) 200 300 0 100 400 500 600 frequency (mhz) 03692-009 hg18 hg127 lg127 figure 9 . noise figure vs. frequency at various gains
ad8370 data sheet rev. b | page 8 of 28 ?8 ?4 0 4 8 12 16 20 output p1db (db) 0 20 40 60 80 100 120 140 gain code 03692-010 unit conversion note: for 100? load: dbv rms = dbm?10db for 1k? load: dbv rms = dbm low gain mode low gain mode high gain mode 100? load 1k? load high gain mode shading indicates 3 from the mean. data based on 30 parts from two batch lots. figure 10 . output p1db vs. gain code at 70 mhz 0 ?90 ?80 ?70 ?60 ? 50 ? 40 ?30 ?20 ?10 ?50 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 0 140 120 100 80 60 40 20 03692-011 gain code low gain mode output imd (dbc) high gain mode output imd (dbc) high gain mode low gain mode figure 11 . two - tone outp ut imd3 vs. gain code at 70 mhz, rl = 1 k?, v out = 2 v p - p composite differential 35 30 25 20 15 10 5 0 ?5 25 20 15 10 5 0 ?5 ?10 ?15 0 140 120 100 80 60 40 20 03692-005 gain code output ip3 (dbm) output ip3 (dbv rms) high gain mode low gain mode figure 12 . output third - order intercept vs. gain code at 70 mhz, r l = 1 k?, v out = 2 v p - p composite differential ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 gain error (db) 1.0 1.5 2.0 frequency (mhz) 10 100 1000 03692-012 ?40c +85c error at ?40c and +85c with respect to +25c. shading indicates 3 from the mean. data based on 30 parts from one batch lot. figure 13 . gain error over temperature vs. frequency, r l = 100 ? 6 8 10 12 14 16 18 20 output p1db (dbm) ?40c, +85c 4 6 8 10 12 14 16 18 output p1db (dbm) +25c 200 150 50 100 0 250 300 350 400 frequency (mhz) 03692-013 shading indicates 3 from the mean. data based on 30 parts from two batch lots. unit conversion note: re 100? load: dbv rms = dbm ? 10db re 1k? load: dbv rms = dbm +25c, 100? load +25c, 1k? load +85c, 100? load +85c, 1k? load ?40c, 100? load ?40c, 1k? load figure 14 . output p1db vs. frequency ?50 ?84 ?82 ?80 ?78 ?76 ?74 ?72 ?70 ?68 ?66 ?64 ?62 ?60 ?58 ?56 ?54 ?52 0 400 350 300 250 200 150 100 50 03692-014 frequency (mhz) output imd (dbc) +85c ?40c +25c figure 15 . two - tone output imd3 vs. frequency at maximum gain, r l = 1 k?, v out = 2 v p - p composi te differential
data sheet ad8370 rev. b | page 9 of 28 34 32 30 28 26 24 22 20 18 16 14 24 22 20 18 16 14 12 10 8 6 4 0 400 350 300 250 200 150 100 50 03692-008 frequency (mhz) output ip3 (dbm) output ip3 (dbv rms) +85c ?40c +25c figure 16 . output third - order intercept vs. frequency at maximum gain, r l = 1 k?, v out = 2 v p - p composite differential ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 gain error (db) 1.0 1.5 2.0 frequency (mhz) 10 100 1000 03692-015 error at ?40c and +85 c with respect to +25c. shading indicates 3 from the mean. data based on 30 parts from one batch lot. ?40c +85c figure 17 . gain error over temperature vs. frequency, r l = 1 k? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 harmonic distortion (dbc) 0 20 40 60 80 100 120 140 gain code 03692-016 high gain, r l = 1k? low gain, r l = 1k? low gain, r l = 100? high gain, r l = 100? figure 18 . second - order harmonic distortion vs. gain code at 70 mhz, v out = 2 v p - p differential 1ghz 5mhz s 22 s 11 0 180 30 330 60 90 270 300 120 240 150 210 03692-017 figure 19 . input and output reflection coefficients, s11 and s22, z o = 100 ? differential 0 50 100 150 200 250 resistance (?) ?150 ?100 ?50 0 50 100 reactance (j ?) 0 100 200 300 400 500 600 700 frequency (mhz) 03692-018 16 different gain codes represented r+jx format fi gure 20 . input resistance and reactance vs. frequency ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 harmonic distortion (dbc) 0 20 40 60 80 100 120 140 gain code 03692-019 low gain r l = 100? low gain r l = 1k? high gain r l = 100? high gain r l = 1k? figure 21 . third - order harmonic distortion vs. gain code at 70 mhz, v out = 2 v p - p differential
ad8370 data sheet rev. b | page 10 of 28 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 harmonic distortion (dbc) 200 150 50 100 0 250 300 350 400 frequency (mhz) 03692-020 hd 2 r l = 100? hd 3 r l = 100? hd 3 r l = 1k? hd 2 r l = 1k? figure 22 . harmonic di stortion vs. frequency at maximum gain, v out = 2 v p - p composite differential 0 20 40 60 80 100 120 resistance (?) ?40 ?20 0 20 40 60 80 reactance (j ?) 0 100 200 300 400 500 600 700 frequency (mhz) 03692-021 16 different gain codes represented r+jx format figure 23 . output resistance and reactance vs. frequency 700 720 740 760 780 800 group delay (ps) 820 840 860 0 10 20 30 40 60 100 50 70 80 90 110 120 130 gain code 03692-022 high gain mode low gain mode figure 24 . group delay vs. gain code at 70 mhz 20 30 40 50 60 70 80 90 100 110 120 psrr (db) frequency (mhz) 1 100 10 1000 03692-023 figure 25 . power supply rejection ratio vs. frequency at maximum gain ?120 ?100 ?80 ?60 ?40 ?20 0 isolation (db) frequency (mhz) 10 100 1000 03692-024 forward transmission, hg0 reverse transmission, hg127 forward transmission, lg0 forward transmission, pwup low figure 26 . various forms of isolation vs. frequency 600 700 800 900 1000 1100 group delay (ps) 1200 1300 1400 0 100 200 300 400 500 600 700 800 900 frequency (mhz) 03692-025 r l = 1k? r l = 100? figure 27 . group delay vs. frequency at maximum gain
data sheet ad8370 rev. b | page 11 of 28 0 10 20 30 40 50 cmrr (db) 60 70 80 frequency (mhz) 10 100 1000 03692-026 hg32, hg127 lg32, lg127 figur e 28 . common - mode rejection ratio vs. frequency 0 2 4 8 10 12 noise spectral density (nv/ hz) 6 210 310 10 110 410 510 610 frequency (mhz) 03692-027 hg18 hg127 lg127 figure 29 . input referred noise spectral density vs. frequency at various gains time (2ns/div) voltage (600mv/div) gnd 03692-028 differential v in differential v out v oplo v ophi figure 30 . dc - coupled large signal pulse res ponse 03692-029 pwup (2v/div) time (40ns/div) gnd zero input = ?30dbm, 70mhz 100 averages gain code hg127 differential output (50mv/div) figure 31 . pwup time domain response 03692-030 ltch (2v/div) time (20ns/div) gnd zero input = ?30dbm, 70mhz no averaging 6db gain step (hg36 to lg127) differential output (10mv/div) figure 32 . gain step time domain response time (2ns/div) voltage (1v/div) 03692-031 gnd v out differential figure 33 . overdrive recovery
ad8370 data sheet rev. b | page 12 of 28 50 55 60 65 70 75 80 85 supply current (ma) 6448 16 32 0 80 96 112 128 gain code 03692-032 high gain low gain figure 34 . supply curren t vs. gain code 0 5 10 15 20 25 30 35 count 50 51 52 53 54 55 gain (v/v) 03692-033 data from 136 parts from one batch lot mean: 51.9 : 0.518 figure 35 . distribution of voltage gain, hg127, 70 mhz, r l = 100 ? 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 v cm (v) 0 96 32 64 0 32 64 96 128 gain code 03692-034 +25c +85c ?40c low gain mode high gain mode figure 36 . common - mode output voltage vs. gain code at various temperatures
data sheet ad8370 rev. b | page 13 of 28 theory of operation the ad8370 is a low cost, digitally controlled, fine adjustment variable gain amplifier (vga) that provides both high ip3 and low noise figure. the ad8370 is fabricated on an adi proprietary high performance 25 ghz silicon bipolar process. the C 3 db bandwidth is approximately 750 mhz throughout the variable gain range. the typical quiescent current of the ad8370 is 78 ma. a power - down feature reduces the current to less than 4 ma. the input impedance is approximately 200 ? differential, and the output impedance is approximately 100 ? differential to be compatible with saw filters and matching networks used in intermediate frequency (if) radio applications. because there is no feedback between the input and output and stage s within the amplifier, the input amplifier is isolated from variations in output loading and from subsequent impedance changes, and excellent input to output isolation is realized. excellent distortion performance and wide bandwidth make the ad8370 a suitable gain control device for modern differential receiver designs. the ad8370 differential input and output configuration is ideally suited to fully differential si gnal chain circuit designs, although it can be adapted to single - ended system applications, if required. block architecture the three basic building blocks of the ad8370 are a high/low gain selectable input pr eamplifier, a digitally controlled transconductance (g m ) block, and a fixed gain output stage. inhi inlo ophi oplo vcco ocom icom vocm pwup vcco ocom vcci icom bias cell shift register and latches pre amp transconductance output amp 11 6 1 16 4 14 13 12 5 9 8 3 2 10 7 15 data clck ltch ad8370 03692-035 figure 37 . functional block diagram preamplifier there are two selectable input preamplifiers. selection is made by the most signific ant bit (msb) of the serial gain control data - word. in the high gain mode, the overall device gain is 7.1 v/v (17 db) above the low gain setting. the two preamplifiers give the ad8370 the ability to accommodate a wide range of input amplitudes. the overlap between the two gain ranges allows the user some flexibility based on noise and distortion demands. see the choosing between gain ranges section for more information. t he input impedance is approximately 200 ? differential, regardless of which preamplifier is selected. note that the input impedance is formed by using active circuit elements and is not set by passive components. see figure 38 for a simplified schematic of the input interface. 1ma 1ma vcc/2 2k ? inhi/inlo 03692-036 figure 38 . inhi/inlo simplified schematic transconductance sta ge the digitally controlled g m section has 42 db of controllable gain and makes gain adjustments within each gain range. the step size resolution ranges from a fine ~ 0.07 db up to a coarse 6 db per bit, depending on the gain code. as shown in figure 39 , of the 42 db total range, 28 db has resolution of better than 2 db, and 22 db has resolution of better than 1 db. figure 39 shows typical input levels that can be applied to this amplifier at different gain settings. the maximum input was determined by finding the 1 db compres sion or expansion point of the v out /v source gain. note that this is not v out /v in . in this way, the change in the input impedance of the device is also taken into account. 0 0.4 0.8 1.2 1.6 2.0 v out [v peak] (v) 2.4 2.8 3.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v source [v peak] (v) 03692-037 high gain 0.1db gain ?5db gain ?8db gain 12db gain 6db gain <2db res <2db res <1db res <1db res <0.5db resolution <0.5db res ?11db gain 17db gain 34db gain ?25db gain low gain figure 39 . gain resolution and nominal input and output r ange over the gain range
ad8370 data sheet rev. b | page 14 of 28 output amplifier the output impedance is approximately 100 ? differential and, like the input preamplifier, this impedance is formed using active circuit elements. see figure 40 for a simpl ified schematic of the output interface. 03692-038 vcc/2 740 ? ophi/oplo figure 40 . ophi/oplo simplified circuit the gain of the output amplifier, and thus the ad8370 as a whole, is load dependent. the following eq uation can be used to predict the gain deviation of the ad8370 from that at 100 ? as the load is varied. load r ion gaindeviat 98 1 98 1 + = . for example, if r load is 1 k?, the gain is a factor of 1.80 (5.12 db) above that at 100 ?, all other things being equal. if r load is 50 ?, the gain is a factor of 0.669 (3.49 db) below that at 100 ?. digital interface an d timing the digital control port uses a standard ttl interface. the 8 - bit control word is read in a serial fashion when the ltch pin is held low. the levels presented to the data pin are read on each rising edge of the clck signal. figure 41 illustrates the timing diagram for the control interface. minimum values for timing parameters are presented in table 4 . figure 42 is a simplified schematic of the digital input pins. data (pin 14) clck (pin 13) ltch (pin 12) t ds t es t eh msb msb-1 msb-2 msb-3 lsb lsb+1 lsb+2 lsb+3 t ck t pw 03692-039 figure 41 . digital timing diagram table 4 . serial programming timing parameters parameter min unit clock pulse width (t pw ) 25 ns cloc k period (t ck ) 50 ns setup time data vs. clock (t ds ) 10 ns setup time latch vs. clock (t es ) 20 ns hold time latch vs. clock (t eh ) 10 ns 10 a clck/data/ltch/pwup 03692-040 figure 42 . simplified circuit for digital inputs 03692-041 vcc/2 75 ? vocm figure 43 . simplified circuit for vocm output
data sheet ad8370 rev. b | page 15 of 28 applications basic connections figure 44 shows the minimum connections required for basic operation of the ad8370 . supply voltages between 3.0 v and 5.5 v are allowed. the supply to the vcco and vcci pins should be decoupled with at least one low inductance, surface- mount ceramic capacitor of 0.1 f placed as close as possible to the device. ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 678 23 5 1 11 10 9 15 14 16 13 12 4 serial control interface 100pf 1nf 0.1 ? f 100pf 0.1 ? f +v s (3.0v to 5.0v) ferrite bead ferrite bead 1nf 1nf 1nf 1nf balanced load r l balanced source r s 2 r s 2 03692-042 figure 44. basic connections the ad8370 is designed to be used in differential signal chains. differential signaling allows improved even-order harmonic cancellation and better common-mode immunity than can be achieved using a single-ended design. to fully exploit these benefits, it is necessary to drive and load the device in a balanced manner. this requires some care to ensure that the common-mode impedance values presented to each set of inputs and outputs are balanced. driving the device with an unbalanced source can degrade the common-mode rejection ratio. loading the device with an unbalanced load can cause degradation to even-order harmonic distortion and premature output compression. in general, optimum designs are fully balanced, although the ad8370 still provides impressive performance when used in an unbalanced environment. the ad8370 is a fine adjustment, vga. the gain control transfer function is linear in voltage gain. on a decibel scale, this results in the logarithmic transfer functions shown in figure 4. at the low end of the gain transfer function, the slope is steep, providing a rather coarse control function. at the high end of the gain control range, the decibel step size decreases, allowing precise gain adjustment. gain codes the ad8370 s two gain ranges are referred to as high gain (hg) and low gain (lg). within each range, there are 128 possible gain codes. therefore, the minimum gain in the low gain range is given by the nomenclature lg0 whereas the maximum gain in that range is given by lg127. the same is true for the high gain range. both lg0 and hg0 essentially turn off the variable transconductance stage, and thus no output is available with these codes (see figure 26). the theoretical linear voltage gain can be expressed with respect to the gain code as a v = gaincode vernier ( 1 + ( pregain ? 1) msb) where: a v is the linear voltage gain. gaincode is the digital gain control word minus the msb (the final 7 bits). ver nier = 0.055744 v/v pregain = 7.079458 v/v msb is the most significant bit of the 8-bit gain control word. the msb sets the device in either high gain mode (msb = 1) or low gain mode (msb = 0). for example, a gain control word of hg45 (or 10101101 binary) results in a theoretical linear voltage gain of 17.76 v/v, calculated as 45 0.055744 (1 + (7.079458 ? 1) 1) increments or decrements in gain within either gain range are simply a matter of operating on the gaincode. six Cdb gain steps, which are equivalent to doubling or halving the linear voltage gain, are accomplished by doubling or halving the gaincode. when power is first applied to the ad8370 , the device is programmed to code lg0 to avoid overdriving the circuitry following it. power-up feature the power-up feature does not affect the gaincode, and the gain setting is preserved when in power-down mode. powering down the ad8370 (bringing pwup low while power is still applied to the device) does not erase or change the gaincode from the ad8370 , and the same gain code is in place when the device is powered up, that is, when pwup is brought high again. removing power from the device all together and reapplying, however, reprograms to lg0.
ad8370 data sheet rev. b | page 16 of 28 choosing between gai n ranges there is some overlap between the two gain ranges; users can choose which one is most appropriate for their needs. when deciding which preamp to use, consider resolution, noise, linearity, and spurious - free dynamic range (sfdr). the most important points to keep in mind are ? the l ow gain range has better gain resolution. ? the high gain range has a better noise figure. ? the high gain range has better linearity and sfdr at higher gains. ? conversely, the low gain range has higher sfdr at lower gains. figure 45 provides a summary of noise, oip3, iip3, and sfdr as a function of device power gain. sfdr is defined as ( ) s nnf iip3 sfdr ??= 3 2 where: iip3 is the input third - order intercept point, the output intercept point in dbm minus the gain in db. nf is the noise figure in db. n s is source resistor noise, C 174 dbm for a 1 hz bandwidth at 300k (27c). in general, n s = 10 log 10 ( ktb ), where k = 1.374 10 ?23 , t is the temperature in degrees kelvin, and b is the noise bandwidth in hertz. ?30 ?20 ?10 0 10 20 noise figure (db); oip3 and iip3 (dbm) 30 40 50 100 110 120 130 140 150 sfdr (db) 160 170 180 ?30 ?20 ?10 0 10 20 30 40 power gain (db) 03692-043 sfdr high gain sfdr low gain oip3 high gain oip3 low gain iip3 low gain iip3 high gain nf high gain nf low gain figure 45 . oip3, iip3, nf, and sfdr variation with gain as the gain increases, the input amplitude required to deliver the same output amplitude is reduced. this results in less distortion at the input stage, and therefore the oip3 increases. at some point, the distortion of the input stage becomes small enough such that the nonlinearity of the output stage becomes dominant. the oip3 does not improve significantly because the gain is increased beyond this point, which explains the knee in the oip3 curve. the iip3 curve has a knee for the same reason; however, as the gain is increased beyond the knee, the iip3 starts to decrease rather than increase . this is because in this region oip3 is constant, therefore the higher the gain, the lower the iip3. the two gain ranges have equal sfdr at approximately 13 db power gain. layout and operating considerations each input and output pin of the ad8370 presents either a 100 ? or 50 ? impedance relative to their respective ac grounds . to ensure that signal integrity is not seriously impaired by the printed circuit board, the relevant connection traces should provide an appropriate characteristic impedance to the ground pla ne. this can be achieved through proper layout. when laying out an rf trace with a controlled impedance, consider the following: ? space the ground plane to either side of the signal trace at least three line - widths away to ensure that a microstrip (vertica l dielectric) line is formed, rather than a coplanar (lateral dielectric) waveguide. ? ensure that the width of the microstrip line is constant and that there are as few discontinuities as possible, such as component pads, along the length of the line. width variations cause impedance discontinuities in the line and may result in unwanted reflections. ? do not use silkscreen over the signal line because it alters the line impedance. keep the length of the input and output connection lines as short as possible. figure 46 shows the cross section of a pc board, and table 5 show the dimensions that provide a 100 ? line impedance for fr - 4 board material with r = 4.6. table 5 . 100 ? 50 ? w 22 mils 13 mils h 53 mils 8 mils t 2 mils 2 mils w 3w e r 3w h t 03692-044 figure 46 . cross - sectional view of a pc board it possible to approxi mate a 100 ? trace on a board designed with the 50 ? dimensions above by removing the ground plane within 3 line - widths of the area directly below the trace.
data sheet ad8370 rev. b | page 17 of 28 the ad8370 contains both digital and analog sections. care should be taken to ensure that the digital and analog sections are adequately isolated on the pc board. the use of separate ground planes for each section connected at only one point via a ferrite bead inductor ensures that the digital pulses do no t adversely affect the analog section of the ad8370 . due to the nature of the ad8370 s circuit design, care must be taken to minimize parasitic capacitance on the i nput and output . the ad8370 could become unstable with more than a few pf of shunt capacitance on each input. using resistors in series with input pins is recommended under conditions of high source capacitance . high transient and noise levels on the power supply, ground, and digital inputs can, under some circumstances, reprogram the ad8370 to an unintended gain code. this further reinforces the need for proper sup ply bypassing and decoupling. the user should also be aware that probing the ad8370 and associated circuitry during circuit debug may also induce the same effect. package consideratio ns the package of the ad8370 is a compact, thermally enhanced tssop 16 - lead design. a large exposed paddle on the bottom of the device provides both a thermal benefit and a low inductance path to ground for the circuit. to make proper us e of this pack - aging feature, the pcb needs to make contact directly under the device, connected to an ac/dc common ground reference with as many vias as possible to lower the inductance and thermal impedance. single - ended - to - differential convers ion ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 serial control interface 0.1f 1nf 0.1f +v s c ac c ac c ac c ac r l single- ended source r s 03692-045 figu re 47 . single - ended -to- differential conversion the ad8370 is primarily designed for differential signal inter - facing. the device can be used for single - ended - to - differential conversion simply by terminating the unused input to ground using a capacitor as depicted in figure 47 . the ac coupling capacitors should be selected such that their reactance is negligible at the frequency of operation. for e xample, using 1 nf capacitors for c ac presents a capacitive reactance of ?j1.6 ? on each input node at 100 mhz. this attenuates the applied input voltage by 0.003 db. if 10 pf capacitors had been selected, the voltage delivered to the input would be reduced by 2.1 db when operating with a 200 ? source impedance. differential balance (db) ?1.0 0 ?0.5 0.5 0 100 200 300 400 500 frequency (mhz) 03692-046 high gain mode (gain code hg255) low gain mode (gain code lg127) figure 48 . differential output balance for a single - ended input drive at maximum gain (r l = 1 k?, c ac = 10 nf) figure 48 illustrates the differential balance at the output for a single - ended input drive for multiple gain codes. the differential balance is better than 0.5 db for signal frequencies less than 250 mhz. figure 49 depicts the differential balance over the entire gain range at 10 mhz. the balance is degr aded for lower gain settings because the finite common gain allows some of the input signal applied to inhi to pass directly through to the oplo pin. at higher gain settings, the differential gain dominates and balance is restored. 0 0.1 0.2 0.3 0.4 0.5 0.6 differential balance (db) 0 96 32 64 0 32 64 96 128 gain code 03692-047 low gain mode high gain mode figure 49 . differential output balance at 10 mhz for a single - ended drive vs. gain code (r l = 1 k?, c ac = 10 nf) even though the amplifier is no longer being driven in a balanced manner, the distortion performance remains adequate for most applications. figure 50 illustrates the harmonic distortion performance of the circuit in figure 47 over the entire gain range.
ad8370 data sheet rev. b | page 18 of 28 if the amplifier is driven in single - ended mode, the inpu t impedance varies depending on the value of the resistor used to terminate the other input as rin se = rin diff + r term where r term is the termination resistor connected to the other input. ?100 ?90 ?80 ?70 ?60 ?50 ?40 harmonic distortion (dbc) 0 96 32 64 0 32 64 96 128 gain code 03692-048 hd2 hd2 low gain mode high gain mode hd3 hd3 figure 50 . harmonic distortion of the ci rcuit in figure 47 dc- coupled operation ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 serial control interface 1nf 1nf 0.1f 0.1f ?2.5v ?2.5v 0v 0v +2.5v r l single- ended ground referenced source r s r t 03692-049 figure 51 . dc coupling the ad8370. dual supplies are used to set the input and output common - mode levels to 0 v. 03692-050 ad8370 ad8138 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 serial control interface 1nf 1nf 0.1f +5v 499? 499? 100? 499? 499? 100? v ocm v ocm v ocm +5v r l single-ended ground referenced source r s r t r t 2 figure 52 . dc coupling the ad8370. the ad8138 is used as a unity - gain level shifting amplifier to lift the common - mode level of the source to midsupply. the ad8370 is also a dc accurate vga. the common - mode dc voltage present at the output pins is internally set to midsupply using what is essentially a buffered resistive divider network connected between the positive supply rail and the common (ground) pins. the input pins are at a slightly higher dc potential, typicall y 250 mv to 550 mv above the output pins, depending on gain setting. in a typical single - supply application, it is necessary to raise the common - mode reference level of the source and load to roughly midsupply to maintain symmetric swing and to avoid sinking or sourcing strong bias currents from the input and output pins. it is possible to use balanced dual supplies to allow ground referenced source and load, as shown in figure 51 . by connecting the vocm pin and unus ed input to ground, the input and output common - mode potentials are forced to virtual ground. this allows direct coupling of ground referenced source and loads. the initial differential input offset is typically only a few 100 v. over temperature, the input offset could be as high as a few tens of mvs. if precise dc accuracy is needed over temperature and time, it may be necessary to periodically measure the input offset and to apply the necessary opposing offset to the unused differential input, cancelin g the resulting output offset. to address situations where dual supplies are not convenient, a second option is presented in figure 52 . the ad8138 differential amplifier is used to translate the common - mode level o f the driving source to midsupply, which allows dc accurate performance with a ground - referenced source without the need for dual supplies. the bandwidth of the solution in figure 52 is limited by the gain - bandwidth product of the ad8138. the normalized frequency response of both implementations is shown in figure 53 .
data sheet ad8370 rev. b | page 19 of 28 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 normalized response (db) 1 10 100 1k 10k 100k 1m 10m 100m 1g frequency (hz) 03692-051 ad8370 with ad8138 single +5v supply ad8370 using dual 2.5v supply figure 53 . normalized frequency response of the two solutions in figure 51 and figure 52 adc interfacing although the ad8370 is designed to provide a 100 ? output source impedance, the device is capable of driving a variety of loads while maintaining reasonable gain and distortion performance. a common application for the ad8370 is adc driving in if sampling receivers and broadband wide dynamic range digitizers. the wide gain adjustment range allows the use of lower resolution adcs. figure 54 illustrates a typical adc interface network. 03692-052 ad8370 v ocm r op 100? c ac z s r ip v in v in r op c ac z s r ip r t z p z in adc figure 54 . generic adc interface many factors need to be considered before defining component values used in the interface network, such as the desired frequency range of operation, the input swing, and input impedance of the adc. ac coupling capacitors, c ac , should be used to block any potential dc offsets present at the ad8370 outputs, which would otherwise consume the available low - end range of the adc. the c ac capacitors should be large enough so that they present negligible reactance over the intended frequency range o f operation. the vocm pin may serve as an external reference for adcs that do not include an on - board reference. in either case, it is suggested that the vocm pin be decoupled to ground through a moderately large bypassing capacitor (1 nf to 10 nf) to help minimize wideband noise pick - up. often it is wise to include input and output parasitic suppression resistors, r ip and r op . parasitic suppressing resistors help to prevent resonant effects that occur as a result of internal bond - wire inductance, pad to s ub strate capacitance, and stray capacitance of the printed circuit board trace artwork. if omitted, undesirable settling characteristics may be observed. typically, only 10 ? to 25 ? of series resistance is all that is needed to help dampen resonant effects. considering that most adcs present a relatively high input impedance, very little signal is lost across the r ip and r op series resistors. depending on the input impedance presented by the input system of the adc, it may be desirable to terminate the adc input down to a lower impedance by using a terminating resistor, r t . the high frequency response of the ad8370 exhibits greater peaking when driving very light loads. in addition, the terminating resistor helps to better define the input impedance at the adc input. any part - to - part variability of adc input impedance is reduced when shunting down the adc inputs by using a moderate tolerance terminating resistor (typically a 1% value is acceptable). after defining reasonable values fo r coupling capacitors, suppressing resistors, and the terminating resistor, it is time to design the intermediate filter network. the example in figure 54 suggests a second - order, low - pass filt er network comprised of series inductors and a shunt capacitor. the order and type of filter network used depends on the desired high frequency rejection required for the adc interface, as well as on pass - band ripple and group delay. in some situations, th e signal spectra may already be sufficiently band - limited such that no additional filter network is necessary, in which case zs would simply be a short and zp would be an open. in other situations, it may be necessary to have a rather high - order antialiasi ng filter to help minimize unwanted high frequency spectra from being aliased down into the first nyquist zone of the adc. to properly design the filter network, it is necessary to consider the overall source and load impedance presented by the ad8370 and adc input, including the additional resistive contribution of suppression and terminating resistors. the filter design can then be handled by using a single - ended equivalent circuit, as shown in figure 55 . a variety of references that address filter synthesis are available. most provide tables for various filter types and orders, indicating the normalized inductor and capacitor values for a 1 hz cutoff frequency and 1 ? l oad. after scaling the normalized prototype element values by the actual desired cut - off frequency and load impedance, it is simply a matter of splitting series element reactances in half to realize the final balanced filter network component values.
ad8370 data sheet rev. b | page 20 of 28 v s r s 2 r s 2 r l 2 r l 2 z s 2 z s 2 z p v s r s r l z s z p source load balanced configuration single-ended equivalent 03692-053 figure 55 . single - ended -to- differential network conversion as an example, a second - order, butterworth, low - pass filter design is presented where the differential load impedance is 1200 ?, and the padded source impedance of the ad8370 is assumed to be 120 ?. the normali zed series inductor value for the 10 - to - 1, load - to - source impedance ratio is 0.074 h, and the normalized shunt capacitor is 14.814 f. for a 70 mhz cutoff frequency, the single - ended equivalent circuit consists of a 200 nh series inductor followed by a 27 p f capacitor. to realize the balanced equivalent, simply split the 200 nh inductor in half to realize the network shown in figure 56 . 03692-054 v s r s 2 r s r l r s 2 r l 2 r l 2 27pf v s r s = 120? r l = 1200? 200nh 100nh 100nh 27pf balanced configuration de-normalized single-ended equivalent v s r s = = 0.1 r l = 1? l n = 0.074h c n 14.814f normalized single-ended equivalent = 60? = 60? = 600? = 600? f c = 70mhz f c = 1hz figure 56 . second - order, butterworth, low - pass filter design example a complete design example is shown in figure 58 . the ad8370 is configured for single - ended - to - differential conversion with the input terminated down to present a single - ended 75 ? input. a sixth - order chebyshev differential filter is used to interface the output of the ad8370 to the input of the ad9430 170 msps, 12 - bit adc. the filter minimizes aliasing effect s and improves harmonic distortion performance. the input of the ad9430 is terminated with a 1.5 k? resistor so that the overall load presented to the filter network is ~1 k ?. the variable gain of the ad8370 ex tends the useable dynamic range of the adc. the measured intermodulation distortion of the combination is presented in figure 57 at 42 mhz. ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?110 ?70 ?50 ?30 ?90 dbfs 0 10 20 30 40 50 60 70 frequency (mhz) 03692-055 figure 57 . fft plot of two - tone intermodulation distortion at 42 mhz for the circuit in figure 58 in figure 57 , the intermodulation products are comparable to the noise floor of the adc. the spurious - free dynamic range o f the combination is better than 66 db for a 70 mhz measurement bandwidth. 3 v operation it is possible to operate the ad8370 at voltages as low as 3 v with only minor performance degradation. table 6 gives typical specifications for operation at 3 v. table 6. parameter typical (70 mhz, r l = 100 ?) output ip3 +23.5 dbm p1db +12.7 dbm ?3 db bandwidth 650 mhz (hg 127) imd3 ?82 dbc (r l = 1 k ?)
data sheet ad8370 rev. b | page 21 of 28 03692-056 ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 serial control interface from 75? tx-line 0.1f 1nf 0.1f +v s 27pf 68nh 180nh 220nh 39pf 27pf 1.5k? 68nh 180nh 220nh 25? 25? c ac c ac 100nf 100nf c ac 100nf c ac 100nf r s 120? v in b ad9430 v in a figure 58 . adc interface example
ad8370 data sheet rev. b | page 22 of 28 evaluation board and software the evaluation board allows quick testing of the ad8370 by using standard 50 ? test equipment. the schematic is shown in figure 59 . transformers t1 and t2 are used to transform 50 ? source and load impedances to the desired inp ut and output reference levels. the top and bottom layers are shown in figure 63 and figure 64 . the ground plane was removed under the traces between t1 and pins inhi and inl o to approximate a 100 ? characteristic impedance. the evaluation board comes with the ad8370 control software that allows serial gain control from most computers. the evaluation board is connected via a cabl e to the parallel port of the computer. adjusting the appropriate slider bar in the control software automatically updates the gain code of the ad8370 in either a linear or linear - in - db fashion. 3 10 12 4 9876 11 5 2 13 1 15 22 24 16 21 20 19 18 23 17 14 25 d-sub 25 pin male ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 2 3 5 1 4 c8 0.1f out+ out? in+ in? c7 0.1f c6 1f c5 0.1f +v s v s gnd gnd p2 vocm pwup c2 c1 t1 1:4 t2 2:1 r2 0? r1 0? r3 0? r4 0? c4 c10 open r8 49.9? r9 open sw1 c3 1nf 1nf 1nf 1nf c9 open l2* l1* r7 1k? r6 1k? r5 1k? 03692-057 tc4-1w 50? tx line 50? tx line 50? tx line 50? tx line jtx-2-10t *emi suppression ferrite hz1206e601r-00 figure 59 . ad8370 evaluation board schematic
data sheet ad8370 rev. b | page 23 of 28 03692-058 figure 60 . evaluation software table 7 . ad8370 evaluation board configuration options component function default condition vs, gnd, vocm power interface vector pins. apply supply voltage between vs and gnd. the vocm pin allows external monitoring of the common - mode input and output bias levels. not applicable sw1, r8, c10, pwup device enable. set to position b to power up the device. when in position a, the pwup pin is connected to the pwup vector pin. the pwup pin allows external power cycling of the device. r8 and c10 are provided to allow for proper cable termination. sw1 = installed r8 = 49.9 ? (size 0805) c10 = open (size 0805) p1, r5, r6, r7, c9 serial control interfaces. the evaluation board can be controlled using most pcs. windows? - based control software is shipped with the evaluation kit. a 25 - pin, d - sub connector cable is required to connect the pc to the evaluation board. it may be necessary to use a capacitor on the clock line, depending on the quality of the pc port signals. a 1 nf capacitor for c9 is usually sufficient for reducing clock overshoot. p1 = installed r5, r6, r7 = 1 k? (size 0603) c9 = open (size 0603) j1, j2, j6, j7 input and output signal connectors. these sma connectors provide a convenient way to interface the evaluation board with 50 ? test equipment. typically, the device is evaluated using a single - ended sour c e and load. the source should connect to j1 (in+), and the load should connect to j6 (out+). not applicable c1, c2, c3, c4 ac coupling capacitors. provide ac coupling of the input and output signals. c1, c2, c3, c4 = 1 nf (size 0603) t1, t2 impedance t ransformers. t1 provides a 50 ? to 200 ? impedance transformation. t2 provides a 100 ? to 50 ? impedance transformation. t1 = tc4 ? 1w (mini - circuits) t2 = jtx ?2? 10t (mini - circuits) r1, r2, r3, r4 single - ended or differential. r2 and r4 are used to ground the center tap of the second ary windings on transformers t1 and t2. r1 and r3 should be used to ground j2 and j7 when used in single - ended applications. r1, r2, r3, r4 = 0 ? (size 0603) c5, c6, c7, c8 l1, l2 power supply decoupling. nominal supply decoupling consists of a ferrite bead series inductor followed by a 1 f capacitor to ground followed by a 0.1 f capacitor to ground positioned as close to the device as possible. c7 provides additional decoupling of the input common - mode voltage. l1 provides high frequency isolation between the input and output power supply. l2 provides high frequency isolation between the analog and digital ground. c6 = 1 f (size 0805) c5, c7, c8 = 0.1 f (size 0603) l1, l2 = hz1206e601r - 00 (steward, size 1206)
ad8370 data sheet rev. b | page 24 of 28 03692-059 figure 61 . evaluation board top silkscreen 03692-060 figure 62 . evaluation board bottom silkscreen 03692-061 figure 63 . evaluation board top 03692-062 figure 64 . evaluation board bottom
data sheet ad8370 rev. b | page 25 of 28 appendix ch aracterization equip ment an agilent n4441a balanced - measurement system was used to obtain the gain, phase, group delay, reverse isolation, cmrr, and s - parameter information contained in this data sheet. with the exception of the s - parameter information, t - attenuator pads were used to match the 50 ? impedance of this instruments ports to the ad8370 . an agilent 4795a spectrum analyzer was used to obtain nonlinear measurements imd, ip3, and p1db through matching b aluns and/or attenuator networks. various other measurements were taken with setups shown in this section. composite waveform a ssumption the nonlinear two - tone measurements made for this data sheet, that is, imd and ip3, are based on the assumption of a fi xed value composite waveform at the output, generally 1 v p - p. the frequencies of interest dictate the use of rf test equipment, and because this equipment is generally not designed to work in units of volts, but rather watts and dbm, an assumption was mad e to facilitate equipment setup and operation. two sinusoidal tones can be represented as v 1 = v sin (2 f 1 t ) v 2 = v sin (2 f 2 t ) the rms average voltage of one tone is ( ) 2 1 1 2 0 1 = dt v t t where t is the period of the waveform. the rms average voltage of the two - tone composite signal is ( ) 1 1 2 0 1 =+ dt vv t t 2 it can be shown that the average power of this composite waveform is twice (3 db) that of the single tone. this also means that the composite peak - to - peak voltage is twice (6 db) that of a single to ne. this principle can be used to set correct input amplitudes from generators scaled in dbm and is correct if the two tones are of equal amplitude and are reasonably close in frequency. definitions of selec ted parameters common - mode rejection ratio ( figure 28 ) has been defined for this characterization effort as gain mode common gain mode al differenti where the numerator is the gain into a differential load at the output due to a differential source at the input, and the denomina tor is the gain into a differential - mode load at the output due to a common - mode source at the input. in terms of mixed - mode s - parameters, this equates to 21 21 sdc sdd more information on mixed - mode s - parameters can be obtained in a reference by bockelman, d.e. and eisenstadt, w.r., combined differential and common - mode scattering parameters: theory and simulation . ieee transactions on microwave theory and techniques, v 43, n 7, 1530 (july 1995). reverse isolation ( figure 26 ) is defined as sdd12. power supply rejection ratio (psrr) is defined as s dm a a where a dm is the differential mode forward gain (sdd21), and a s is the gain from the power supply pins (vcci and vcco, taken together) to t he output (oplo and ophi, taken differentially), corrected for impedance mismatch. the following reference provides more information: gray, p.r., hurst, p.j., lewis, s.h. and meyer, r.g., analysis and design of analog integrated circuits , 4 th edition , john wiley & sons, inc., page 422.
ad8370 data sheet rev. b | page 26 of 28 03692-063 ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 1f 1f t1 t2 0? 1nf 1nf 1nf 1nf 1nf 1nf 1nf mini- circuits tc4-1w v s 5.0v v s 5.0v v s 5.0v serial data source agilent 8753d network analyzer mini- circuits tc2-1t ?22.5db port 1 port 2 figure 65 . psrr a dm test setup 03692-064 ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 200? 1nf 1nf 1nf 1nf 1nf serial data source agilent 8753d network analyzer mini- circuits tc2-1t port 1 port 2 bias tee connection to port 1 figure 66 . psrr a s test setup 03692-065 ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 1f 50? input aux in tektronix tds5104 dpo oscilloscope hp8133a 3ghz pulse generator 50? input 50? input 50? input 475? 200? 52.3? 52.3? 475? 1f 1nf 1nf 1nf v s 5.0v 2db atten 2db atten 3db atten 3db atten trig out out 6db splitter 3db atten 3db atten 6db splitter v s 5.0v v s 5.0v serial data source figure 67 . dc pulse response and overdrive recovery test setup
data sheet ad8370 rev. b | page 27 of 28 03692-066 ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 1f 475? 475? 105? 1f t1 t2 0? 1nf 1nf 1nf 1nf 1nf 1nf 1nf mini- circuits tc4-1w v s 5.0v v s 5.0v v s 5.0v serial data source mini- circuits jtx-2-10t agilent 8648d signal generator rf out 50? input 50? input tektronix tds5104 dpo oscilloscope tektronix p6205 active fet probe figure 68 . gain step time domain response test setup 03692-067 ad8370 inhi icom vcci pwup vocm vcco ocom ophi oplo ocom vcco ltch clck data icom inlo 6 7 8 2 3 5 1 11 10 9 15 14 16 13 12 4 1f 52.3? 475? 475? 105? 1f t1 t2 0? 1nf 1nf 1nf 1nf 1nf 1nf 1nf mini- circuits tc4-1w v s 5.0v v s 5.0v v s 5.0v serial data source mini- circuits jtx-2-10t agilent 8648d signal generator rf out agilent 33250a function/arbitrary waveform generator output 10mhz in 10mhz ref out 50? input 50? input tektronix tds5104 dpo oscilloscope tektronix p6205 active fet probe figure 69 . pwup response time domain test setup
ad8370 data sheet rev. b | page 28 of 28 outline dimensions compliant t o jedec s t andards mo-153-abt 050806- a 16 9 8 1 exposed p ad (pins up) 5.10 5.00 4.90 4.50 4.40 4.30 6.40 bsc top view bot t om view 0.65 bsc 0.15 0.05 coplanarit y 0.10 1.20 max 1.05 1.00 0.80 0.30 0.19 sea ting plane 0.20 0.09 3.05 3.00 sq 2.95 8 0 0.75 0.60 0.45 figure 70 . 16 - lead thin shrink small outline package wi th exposed pad [tssop_ep] (re - 16 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad8370are - reel7 C 40 c to +85 c 16- lead tssop _ep , 7 tape and reel re -16 -2 ad8370arez C 40 c to +85 c 16- lead ts sop _ep , tube re -16 -2 ad8370arez - rl7 C 40 c to +85 c 16- lead tssop _ep , 7 tape and reel re -16 -2 ad8370 - eval z evaluation board 1 z = rohs compliant part . ? 2005 - 2011 analog devices, inc. all rights reserved. trademarks and regist ered trademarks are the property of their respective owners. d03692 C0C 12 /11(b)

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